1. Technical Field
The embodiments described herein generally relate to a highly integrated phase change memory device and a method for manufacturing the same and, more particularly, to a highly integrated phase change memory device having a micro-sized diode and a method for manufacturing the same.
2. Related Art
Generally, semiconductor memory devices are classified as volatile semiconductor memory devices, such as a DRAM device or an SRAM device, which cannot retain data stored if power to the devices is shut off, and non-volatile semiconductor memory devices, such as an EEPROM device, which can retain data stored even if power is shut off to the devices. A flash memory device, which is classified as a non-volatile semiconductor memory device, is used primarily for electronic appliances such as digital cameras, mobile phones, or MP3 players. However, new semiconductor memory devices, such as an MRAM (magnetic RAM) device, an FRAM (ferroelectric RAM) device, and a PRAM (phase change RAM) device have been developed to replace flash memory devices since flash memory devices requires a lot of time to record or read data.
Among those semiconductor memory devices mentioned above, the PRAM device stores data using a difference in resistance between an amorphous state and a crystal state resulting from phase transition of a chalcogenide compound. The PRAM device stores data as a “0” and “1” based on a reversible phase transition of a phase change material layer including the chalcogenide compound Ge—Sb—Te (GST) according to an amplitude and a length of a pulse applied thereto. More specifically, a reset current is required for transitioning the phase change material layer into the amorphous state that has a higher resistance and a set current is required for transitioning the phase change material layer into the crystal state that has a lower resistance. The reset and set currents are transferred to the phase change material layer via a switching device and a lower electrode contact that are positioned below the phase change material layer to activate the phase change.
Recently, as with other memory devices, the phase change memory device has become more highly integrated and a vertical diode having an area narrower than that of a transistor is employed in the phase change memory device as a switching device.
Hereinafter, a method for manufacturing a vertical diode used in a conventional phase change memory device will be described with reference to FIGS. 1a to 1c and 2a to 2c. 
Referring to FIGS. 1a and 2a, a semiconductor substrate 10 having a cell area A and a peripheral area B is prepared. An n-type impurity region 15 is then formed in the cell area A. A gate material layer (not shown) is subsequently formed on the semiconductor substrate 10 having the impurity region 15. After formation of the gate material layer, the gate material layer is partially removed such that the gate material layer remains on the peripheral area B to form a gate electrode 20.
Referring to FIGS. 1b and 2b, an interlayer dielectric layer 25 is formed on the semiconductor substrate 10. A mask pattern 30 having a plurality of openings 32 is then formed on the interlayer dielectric layer 25 to expose portions of the impurity region 15 formed in the cell area A. The openings 32 determine the size of the diode to be formed later. Accordingly, the openings 32 must be arranged having a small pitch with small diameters so that a maximum number of openings 32 can be formed in the cell area A.
As shown in FIGS. 1c and 2c, the interlayer dielectric layer 25 is etched using the mask pattern 30 as an etch mask to form contact holes H for exposing the impurity region 15. An SEG (selective epitaxial growth) layer 40a is then grown to fill the contact holes H with the SEG layer 40a. The SEG layer 40a serves as an n-type impurity layer since the SEG layer 40a is grown from the n-type impurity region 15. Then, p-type impurities are implanted into the n-type SEG layer 40a to form a p-type impurity region 40b and thereby forming a PN diode 40.
As mentioned above, according to the conventional phase change memory device, the diode contact holes H must be arranged at a small pitch with small diameters to obtain a highly integrated phase change memory device. In the typical phase change memory device, a unit cell of the cell area A has an area of 1F2, which is smaller than an area (6F2) of a unit cell for a DRAM device. As a result, there has been suggested a method of using a quadrupole type aperture (not shown) to form the contact holes of the phase change memory device because the quadrupole type aperture exhibits a higher optical efficiency than that of a dipole type aperture used for forming storage node contact holes of the DRAM device. In other words, although the dipole type aperture is advantageous in supplying light over a relatively large area, a smaller amount of light is supplied to a narrow area. For this reason, if the diode contact hole mask pattern 30 of the phase change memory device is formed using the dipole type aperture, the interlayer dielectric layer 25 cannot be sufficiently exposed.
Meanwhile, a large amount of light can be supplied to the semiconductor substrate using the quadrupole type aperture. The amount of light supplied using the quadrupole type aperture is approximately two times greater than the amount of light supplied to the semiconductor substrate using the dipole type aperture. Thus, a relatively greater amount of light can be supplied to the narrow area if the quadrupole type aperture is adopted in the phase change memory device. As a result, the mask pattern 30 can sufficiently expose the interlayer dielectric layer 25. However, if an upper side of the mask pattern 30 is excessively exposed to the light, the mask pattern 30 may become deformed so that the shape of the contact hole may become deformed (see, FIG. 1c).
Additionally, as mentioned above, since the diode contact hole H is formed in a relatively narrow area (1F2), the contact hole may be affected by the light used for forming an adjacent contact hole. Such a phenomenon is called a “side robe phenomenon”. When the side robe phenomenon occurs, a dummy contact hole H1 may form in an undesired region. If a dummy contact hole H1 is formed as mentioned above, a diode is formed in the dummy contact hole H1. This causes an electrical defect with respect to a normal diode adjacent to the diode.